Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems

摘要

With ever-increasing CPU speeds, the need for higher bandwidth memory systems is greater than ever. With signaling rates up to 800Mbs, DDR2 memory technology provides the required bandwidth and growth path needed for current and next generation CPUs and systems. Signal integrity, timing, and crosstalk analysis on these interfaces has become significantly more complex than for previous DDR1 technology. Historic analysis approaches do not properly calculate margin, thereby forcing costly over-design, system over-constraint, reduced margin, or reduced performance. This paper highlights key issues that must be incorporated into the design methodology for engineers performing pre-layout solution space analysis to identify topology and termination schemes or post-layout verification to validate physical implementation of DDR2 designs.