Three-Dimensional Integrated Circuits Overcome Technical Limitations Inherent to Systems-in-Package

摘要

The debate about SoC versus SiP can create an impression that the two approaches are interchangeable and that the details of a specific application simply tilt the decision one way or the other. In reality the approaches are fundamentally different in economic terms - such as time to market, NRE, and unit cost etc. - as well as in technical terms - power efficiency, form factor, bandwidth, etc. These differences are so fundamental that often either choice is a "force fit". Because of this "Rules of Thumb" about domains of application are dangerous, but generally speaking SIP is used where Development Cost and time to market are dominant concerns and SoC is used where power efficiency and performance dominate. This paper will present the technical and business rationale for a new option, a 3D SoC. The 3D SoC provides single die performance and economics but uses a SiP-like design methodology. We will emphasize how the 3D chip approach impacts the cost of design, the length of the design cycle, design reuse and design risk. We will also show how the 3D SoC methodology addresses key technical challenges facing the industry today - such as power dissipation, high bandwidth performance, and form factor. The analysis will be presented as a 3-way comparison of conventional SoC, SiP and 3D SoC and will project how these technologies will share in future markets.