'Fearless Partitioning': An efficient Approach to the Challenges of a true multi-chip integration into a single SOC

摘要

This paper presents a design methodology with associated implementation techniques that helps cope with the complexity of integrating existing parts into a single die. Its key characteristics are: "no restriction in netlist partitioning", "relative floorplanning," "Decorrelation of chip level timing closure from block level timing closure by alignment of clocks in a central layout Clock Generation Unit," "sign-off constraints generic to hierarchy changes", "Multi-level Formal verification." These techniques have successfully been applied on a complex SoC built from 4 existing devices together with additional new functionality. It was demonstrated that "breaking the logical hierarchy" to better fit the physical implementation can lead to significant advantages. Combined with "correct by construction" approach and optimized floorplanning methods, it can facilitate fast automatic iterations and improve time to market drastically.