Customized Synthesis for 90 nm Structured ASICs-Delivering Higher Performance, Faster Time to Market and Reduced Work on the Back End

摘要

Structured ASIC architectures were designed to reduce and even eliminate some of the most challenging issues facing cell-based ASIC designers, including test, power consumption and clock distribution, resulting in shorter design cycle times. This hands-on tutorial will focus on the technical details of how structured ASIC technology, such as NEC Electronics' ISSP architecture, and optimized physical synthesis design tools, such as Synplicity's Amplify ISSP synthesis software can affect the design flow by minimizing or eliminating back-end design problems, such as signal and power integrity, that become more prominent as designers migrate to the 90 nm technology node.