Wireability Comparison of Flip Chip Substrates as a Function of Chip Design and Substrate Capability

摘要

As flip chip grows in usage it becomes increasingly important to determine the wiring capability of flip chip substrates as a function of chip design and substrate capability. This paper defines a flip chip standardized footprint that allows comparisons to be made for the key variables. The footprint has a mix of signal and power I/Os with the signal escape that can best be classified as peripheral. It then explores the major variables that the designer has available including flip chip bump pitch, chip size, substrate layer count, substrate build-up layer density, substrate core layer density plus substrate via and plated through hole capability. The end result is a set of graphs that show wiring capability vs. chip size for the variables that have been examined. These graphs can be used by the designer to determine the chip size and substrate capability required to execute the design in the most efficient manner. The substrates used in this study are of the build-up variety and a key variable that is explored is the density of the core plated through holes. Chip bump pitch is explored from 150 μm thru 225 μm and chip size from 6 mm through 18 mm. Substrate build-up layers of one through six are included. In all cases, the signal lines maintain nearby reference planes for good electrical performance. The paper will also go through the substrate design steps layer by layer with an objective to provide maximum wiring capability using the available design parameters. The results of this study can help the designer achieve the most cost effective combination of chip design and substrate selection while maintaining good electrical performance. This allows effective co-design of the chip and substrate which can significantly reduce the cycle time for new products.