首页> 外文会议>American Society for Engineering Education Annual Conference and Exposition >Presenting Test Benches and Device Characteristics of Programmable Logic In An Introductory Logic Circuits Course
【24h】

Presenting Test Benches and Device Characteristics of Programmable Logic In An Introductory Logic Circuits Course

机译:介绍逻辑逻辑电路课程中可编程逻辑的测试台和设备特征

获取原文

摘要

In the fall semester of 2011, we introduced the complex programmable logic device (CPLD) in our introductory logic circuits course. We specifically chose to use a CPLD as it is a modern logic device and includes the use of modern CAD tools and allows for hands-on activities. This paper considers test benches as well as CMOS device characteristics which are each important to the students' learning experience about CPLDs. In our prior research we identified test benches as a critical aspect in the use of logic circuit CAD tools. This paper first outlines our effort to better introduce students to test benches. Previously, in teaching with traditional TTL logic, the presentation of device characteristics such as signal Voltage levels, device loading, and propagation delay was immediately available. With the move of other educators from such a hands-on, to a hands-off approach using a development board, the presentation of device characteristics appears to be missing from the curriculum. In using our CPLD module we are discovering ways, in the context of CMOS devices, to introduce long standing basic concepts back into our introductory logic circuits course. Students in such an introductory course must be aware that they are dealing with real circuits and that logic signals are represented with physically measurable quantities. The logic circuits lab must be tangible, demonstrating the connection between digital and analog concepts, such as Voltage and current. Our students take their first electric circuits course the same semester as introductory logic circuits which means that these ideas are new to our students. As such we limit our discussion to presenting the device characteristics of logic circuits. The device characteristics of CMOS gates differ from traditional TTL devices in several important ways. Students discover that for CMOS the transition region between logic high and logic low is extremely narrow which causes a gate to be sensitive to noise present in a slowly changing input. Given such sensitivity, this paper presents a feedback test circuit useful for investigating the transition region. Also, given that some CPLDs include Schmitt trigger capability, our students investigate how such capability reduces sensitivity to noise. Students also learn about propagation delay and static loading such as that with an LED. In performing our research we assessed our students' learning experience with our test bench tutorial content, and assessed how device characteristics should be included in our course. We include results and analysis from a student focus group, an anonymous exit survey, and include our own observations.
机译:在2011年秋季学期,我们在介绍性逻辑电路课程中引入了复杂的可编程逻辑设备(CPLD)。我们专门选择使用CPLD,因为它是现代逻辑设备,包括使用现代CAD工具,并允许动手活动。本文考虑了测试台以及CMOS设备特征,这些特征对学生的学习经验有关CPLD。在我们的先前研究中,我们将测试台作为使用逻辑电路CAD工具的关键方面。本文首先概述了我们努力更好地将学生引入测试长椅。以前,在具有传统TTL逻辑的教学中,立即提供诸如信号电压电平,器件加载和传播延迟的器件特性的呈现。随着其他教育者从这种动手移动,通过开发板的脱离方法,课程似乎缺少了设备特征的演示。在使用我们的CPLD模块时,我们在CMOS设备的上下文中发现了方法,将长期站立的基本概念引入我们的介绍性逻辑电路课程。在这种介绍性课程中的学生必须意识到它们处理实际电路,并且该逻辑信号用物理可测量的数量表示。逻辑电路实验室必须有形,展示数字和模拟概念之间的连接,例如电压和电流。我们的学生将他们的第一个电路课程与介绍性逻辑电路相同,这意味着这些想法对我们的学生来说是新的。因此,我们将我们的讨论限制为呈现逻辑电路的设备特性。 CMOS栅极的器件特性以几种重要方式与传统TTL器件不同。学生发现,对于CMOS,逻辑高和逻辑低之间的过渡区域非常窄,这使得门对缓慢改变输入中存在的噪声敏感。考虑到这样的灵敏度,本文提出了一种用于研究过渡区域的反馈测试电路。此外,鉴于某些CPLD包括Schmitt触发能力,我们的学生调查这种能力如何降低对噪声的敏感性。学生还了解传播延迟和静态加载,例如带有LED。在执行我们的研究时,我们通过测试台辅导内容评估了学生的学习经验,并评估了如何在我们的课程中包含设备特性。我们包括学生焦点小组的结果和分析,匿名退出调查,包括我们自己的观察。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号