Correlated Noise Modeling and Simulation

摘要

This paper addresses several issues in noise modeling and simulation. It shows how correlated noise can be implemented in Verilog-A, and presents a new and simple technique to simulate the noise correlation coefficient using only the standard Spice noise analysis. An analytic proof is given that the noise contributed by the distributed gate resistance of a MOSFET can be modeled by including a resistance of value R{sub}g/3 in series with the gate capacitance, which serendipitously provides good low frequency AC modeling. Analysis of series and parallel combinations of devices is done to derive fundamental geometric scaling relations for noise. Finally, implementation of correlated MOSFET gate in Verilog-A is demonstrated, and it is shown that the gate noise must be distributed between gate-source and gate-drain components to maintain proper symmetry.