Estimating adders for a low density parity check decoder

摘要

Low density parity check decoders use computation nodes with multioperand adders on their critical path. This paper describes the design of estimating multioperand adders to reduce the latency, power and area of these nodes. The new estimating adders occasionally produce inaccurate results. The effect of these errors and the subsequent trade-off between latency and decoder frame error rate is examined. For the decoder investigated it is found that the estimating adders do not degrade the frame error rate.