High Speed Timing Analysis Using IBIS Models Techniques for Relating the Data Sheet to the Final PCB Environment

摘要

Demand for performance and ever higher external interface speeds place significant pressure on reducing design timing margins. Understanding the timing relationships between the final application boards, and data sheet reference loads is critical to extracting maximum performance out of a given interface. This paper presents techniques using IBIS models to relate the customer's expected environment to the datasheet reference environment. Also examined is the effect of board loading on maximum interface speed and device/board design difficulty.