This paper describes a DS-3, OC-3, OC-12, and OC-48 to OC-192 aggregation reference card that was designed with a 7-week schedule requirement. It details the approach we took to meet this requirement and provides insight into some of the key issues we encountered. Some of the topics covered are how we partitioned the design to allow concurrent engineering, how the design allowed software to leverage existing code, tips on reducing the printed circuit board design schedule, and high-speed power distribution recommendations for ultimate performance. Design measurements are provided.
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