Rapidly incorporating modules is fundamental for modern digital systems design. Even though, the design of interface process and bus wrappers can be a difficult and error prone task due to the physical design complexity and the diversity of existing interface patterns. Design, simulation and analysis of transceivers between modules with different interface protocols can be facilitated with the use of a powerful and transparent methodology based on a Petri Net modelling. This work addresses an interface process synthesis methodology based on Petri Net which allow a fast coupling of new components in a bus with further analysis, verification and implementation mechanisms. We focus specially at system level module integration on System-on-a-Programmable-Chip(SoPC) environments.
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