A Modeling Methodology for Reliability Evaluation of Hw/Sw Co-Design: An Approach based on DSPN and Fault Tolerance

摘要

The introduction of fault tolerance mechanisms into co-design methodology for embedded systems, imposes solutions for quantitative and qualitative analysis, simultaneously. This paper proposes a methodology to compute fault tolerant attributes, in special, reliability, taking into account the coverage factor, through a stochastic Petri net models. By means of the proposed methodology, static and dynamic redundancies applied to fault tolerant embedded systems are analyzed and insights about reliability are obtained for a system design, allowing the user to abstract himself/herself from formal analysis and to concentrate on his specific application.