OVERMOLDED BALL GRID ARRAY MATERIALS, DESIGN, AND PROCESSING INFLUENCE ON PACKAGE FLATNESS FOR RELIABLE SURFACE MOUNT

摘要

Chip manufacturers are increasingly challenged to assemble ball grid array packages at finer wire pitches that can withstand higher temperature reflow peaks, and still reliably mount on a board. New encapsulant materials developed for finer pitch geometries must also meet increased thermal loads in package manufacturing and testing, which are necessary to guarantee the package integrity and functionality. The interaction of the package configuration and the encapsulant material properties with the increased thermal loads must be assessed thoroughly both during and after assembly. An applicable method to assess package flatness and coplanarity at the various thermal load stages of package processing must be devised to predict a customer's ability to successfully board mount the package. This paper will address the effects of the newer fine pitch encapsulant material properties and the increasing thermal loads during assembly molding, post-mold cure, burn-in, and high temperature reflow. Package flatness evaluations will demonstrate and rank the impact of particular attributes, including body size, mold cap thickness, and encapsulant material properties. Moreover, it will be shown how critical material and package development must include assessment of package flatness at reflow temperature to assure solderability.