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Ultra-Thin Silicon (UTSI) On Insulator CMOS ransceiver and Time-Division Multiplexed Switch Chips for Smart Pixel Integration

机译:超薄硅(UTSI)在绝缘体CMOS Ransceiver和时分复用开关芯片,用于智能像素集成

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We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon (UTSi) on insulator technology. The Peregrine UTSi silicon-on-sapphire (SOS) technology is a member of the silicon-on-insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on-chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will equire monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor-metal (MSM) or GaAs p-i-n detector die arrays to achieve high-speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).
机译:我们描述了基于绝缘技术的Peregrine半导体超薄硅(UTSI)的两种不同0.5微米CMOS光电集成电路(OEIC)芯片的设计,制造和功能。 Peregrine UTSI Silicon-On-Sapphire(SOS)技术是绝缘体(SOI)家族的成员。低损耗合成蓝宝石基板是光学透明的,具有良好的导热性和热膨胀性能系数,其符合VCSELS和其他光电输入输出组件的倒装芯片键合的要求。一芯片包含收发器和网络组件,包括四个通道高速CMOS收发器模块,伪随机比特流(PRB)发生器,电压控制振荡器(VCO)和其他测试电路。收发器芯片可以以自测模式和网络模式运行。片上时钟和真正的相位时钟(TSPC)D-FLIP-FLOP旨在为高速收发器阵列产生超过2.5 GB / s的PRB,以便在自测试模式下运行。在网络模式中,偶数数量的收发器芯片通过自由空间或光纤互连形成环网络。第二芯片包含四个通道光学时分多路复用(TDM)开关,光收发器阵列,有源像素检测器和附加测试设备。这些芯片的最终应用将使整体OEIC具有集成光输入和输出。制造和测试之后,CMOS收发器阵列芯片将被封装在850nm垂直腔表面发射激光器(Vcsels)和金属半导体 - 金属(MSM)或GaAs P-I-N检测器模具阵列中,以实现高速光学互连。混合技术可以是CMOS SOS SMOS SMOS智能像素阵列的引线键合或倒装芯片键合,其中VCSELS和光电探测器作为多芯片模块(MCM)上的光电芯片载体上。

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