Development of a Configurable Architecture for Smart Pixel Research (CASPR)

摘要

The design, demonstration and evaluation of a general purpose, smart pixel based photonic information processing unit is presented. Based on a photonic VLSI device technology that can be implemented using a standard 1.5-μm CMOS, each pixel incorporates a photoreceiver with a RISC processor and produces a device that is suitable for prototyping photonic information processing systems.