We examine the architecture of α-Coral, which supports multithreaded execution on a single chip processor, α-Coral simultaneously executes multiple threads which are generated by a parallelizing compiler. By using dedicated instructions for thread control, α-Coral handles multi-grained threads. The same instructions enable threads to communicate with each other efficiently via shared registers. Earlier we have been evaluating the architecture using a software simulation. In this paper we conduct logical synthesis of it by Hardware Description Language (HDL) in order to confirm the validity of the architecture.
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