Evaluation of MOSFET Characteristics with Thick Interconnection Formed by Gold Electroplating for Seamless Integration Technology

摘要

This paper describes new thick gold multilevel interconnection techniques and the effect of such thick Au interconnections on underlying LSIs. Line-pillar vias were made by Au electroplating and the planarizcd multiple intcrlayer dielectrics (ILDs) were made by a spin-coating film transfer and hot-pressing (STP) technique at the same time without using conventional damascene processes. The effect of stress due to the thick Au layer on device characteristics for CMOSFETs was also investigated. The thick Au layer does not deteriorate the characteristics of the underlying MOSFETs. These results confirm that the thick interconnect format ion by STP and the An electroplating is applicable to the fabrication of thick multilevel interconnects.