In the semiconductor manufacturing, the fabrication process is the most technology-intensive and complicated one. The fabrication process requires longer cycle time than the subsequent probe, assembly and final test processes because of difficulties and complexity of the lot flow. The photolithography area, where wafers are processed on coaters, aligners and developers, typically comprises the bottleneck workstation. It is thus very crucial to develop schedules that ensure maximum utilization of equipment, as well as the production target within given cycle time. The operational performance of the semiconductor fabrication line is known to be affected by the input and bottleneck scheduling policies. We have suggested input and scheduling rules, which are expected to achieve good performance of throughput, machine utilization, and cycle time reduction. These rules are tested on the computational simulation model in which wafers flow layer to layer, each layer consisting of bottleneck and non-bottleneck. This simulation model successfully represents the wafer flows of real fabrication line. We have shown that scheduling rules are more sensitive than the input rules in throughput and utilization. Balance oriented rules and the throughput oriented rules are compared in several performance measures, and throughput oriented rules are shown to be robust whatever the WIP balance is.
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