It is widely recognized that future multiprocessor computer architectural concepts must overcome the limitations of traditional metallic buses and backplanes to achieve high overall performance. problematic inter-processor communications bottlenecks can be found in a broad range of significant applications - from large telecom/datacom switches to multiprocessor signal and image processing applications. With smart pixel throughput capabilities projected to exceed 1 Tbit/s/cm~2, it is hoped that they may be incorporated into a new generation of multiprocessor architectures that will overcome multiprocessor communications bottlenecks.
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机译:众所周知,未来的多处理器计算机架构概念必须克服传统金属公共汽车和背板的局限性,以实现高整体性能。有问题的处理器间通信瓶颈可以在广泛的重要应用中找到 - 从大型电信/ Datacom开关到多处理器信号和图像处理应用。使用智能像素吞吐量,投影超过1 Tbit / s / cm〜2,希望它们可以纳入新一代的多处理器架构,这些架构将克服多处理器通信瓶颈。
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