Transaction Level Modeling (TLM) captures abstract models of Systems-on-Chip that simulate faster than traditional RTL simulations and are available earlier in the design flow. Such models allow the development of the embedded software on a virtual prototype of the hardware, before the chip is available. Various levels of details in TL models are needed; using untimed and timed models for different purposes is a usual practice. We present a method for developing very abstract untimed models first, and then enriching them to get detailed timed models, while preserving the functionality. The timed models can be as rich as the models usually written from scratch. The experiments with industrial case-studies show improved simulation speed and reduced modeling effort for both untimed and timed models.
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