The thermal resistance at the interface of a VLSI die and its carrier strongly contributes to the total temperature rise in the electronic packaging system. This die-attach thermal resistance is made nonhomogeneous and difficult to predict byvoiding and delamination at the interface. In addition, the thermal resistance may not remain constant during the lifetime of a product when the interface degrades under high humidity or thermal cycling. This manuscript develops a technique for preciselymeasuring die-attach thermal resistance. The technique uses electrical heating and thermometry at frequencies from 10 to 10{sup}3 Hz and evaluates the spatial variation of the thermal resistance through photothermal imaging. The use of varying heatingfrequencies helps minimize the uncertainty in the resistance to a value near 10{sup}(-6) m{sup}2K/W. In contrast to DC methods, the present technique is not influenced by the thermal boundary conditions for the die carrier. Data are provided for samplesfabricated using varying adhesive materials and their quantities and attachment pressures.
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