Impact of MCM's on high performance processors

摘要

Researchers at the University of Michigan, in collaboration with their partners from Motorola and Cascade Design Automation, are developing design methodologies and automated tools for use in implementing high clock rate digital"systems-on-an-MCM." The PUMA processor, a demonstration vehicle that executes a subset of the PowerPC instruction set, will be designed to operate with a 1 GHz clock. The PUMA will be implemented as a system-on-an-MCM from a set of complementary GaAs(CGaAs) chips that employ area interconnect for high bandwidth inter-chip connections on the MCM. In particular, the paper discusses design tools for systems-on-an-MCM, the optimization of inter-chip drivers, and techniques for optimizing the systemperformance given the delay of inter-chip crossing.