This paper presents a design methodology for the development of Application Specific Integrated Circuits (ASICs) that provides flexibility in the selection of a target implementation methodology and foundry. The paper also describes the advantages of migrating from one technology to another; specifically from a field or electrically programmable array device to a mask programmable device in order to reduce silicon area for cost and performance improvements. Additional information will show how multiple user-programmable parts can be combined into a single mask programmable part further reducing costs.
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