Recent advances in ultra-thin silicon-on-insulator (SOI) technology have made partially depleted (PD)-SOI-CMOS a promising candidate for use in high-speed circuits. However, some breakthroughs must still be made, the most important of which would be understanding and control of hysteretic behavior. Some hysteretic characteristics have been analyzed, and some methods to suppress this behavior have been proposed (Assaderaghi et al., 1994; Houston et al., 1998; Maeda et al., 1998; Wei et al., 1998; Pelella et al., 1999). However, the operation-period dependent circuit-delay is not sufficiently understood. In this paper, closed form analysis was used to analyze the operation-period-dependent circuit delay, and the results were confirmed with circuit simulators.
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