PERFORMANCE-CONSTRAINED PARASITIC-AWARE RETARGETING AND OPTIMIZATION OF ANALOG LAYOUTS

摘要

Performance of analog circuits is highly sensitive to layout parasitics. This paper presents an improved algorithm that automatically conducts performance-constrained parasiticaware retargeting and optimization of analog layouts. In order to meet the desired circuit specification, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies sensitivity-based model to control parasitic-related layout geometries by constructing a set of performance constraints subject to maximum performance deviation due to parasitics. The formulated problem is finally solved using graph-based techniques and nonlinear programming. The algorithm has been demonstrated to be effective and efficient by successfully retargeting several operational amplifiers within minutes of CPU time.