Macromodel of G~4FET Enabling Fast and Reliable SPICE Simulation for Innovative Circuit Applications

摘要

A macromodel of silicon-on-insulator (SOI) four-gate transistor (G~4FET) is presented in this paper to aid circuit designers to explore innovative applications circuit with this multi-gate transistor. A number of works based on analytical solution, numerical simulation and experimental results of G~4FET have been previously reported. However, designing new interesting circuits with G~4FETs requires a SPICE model that will work sufficiently well throughout the desired operating regions. Although it is theoretically possible to solve coupled non-linear differential equations to explore different operating conditions, this will take an excessive amount of time making it unsuitable for useful circuit design. Therefore, a macromodel approach is adopted in this work to provide a reasonably fast and accurate circuit simulation. G~4FET combines the functionality of MOSFET and JFET devices which already have robust, fast and reliable SPICE models. A macromodel approach which is capable of combining these existing models including the interactions between multiple gates will be beneficial for any circuit designer. The feasibility of the macromodel is justified by simulating several analog and digital circuits and comparing against available experimental results.