Interface Engineering of High-k Dielectrics and Metal Contacts for High Performance Top-gated MoS_2 FETs

摘要

A combination of contact and gate dielectric engineering is utilized to achieve very high performance few layer MoS_2 FET. Sulfur treatment before the formation of Ni and Pd source/drain contacts helps in reducing the schottky barrier height and thereby resulting in 10x reduction in contact resistance. The e-beam evaporated 30nm HfO_2 gate dielectric, with optimized processing condition, yields 6.1nm EOT, with interface trap density in the mid 10~(11)/cm~2 range. The top gated MoS_2 FET demonstrates field effect mobility of 63 cm~2/V-sec. This FET is used along with a depletion mode n-channel FET load, to demonstrate inverter circuit characteristics with output to input gain of 9.