Adopt advanced RDL Rule to Apply Flipchip Technology For Next Generation Si Technology: Feasibility Study

摘要

With silicon node technology shrinking to beyond 14nm, die pad pitch becomes smaller and bumps become finer dimensioned so that I/O pads can be laid out. In many cases, flip chip assembly is required because of layout considerations, performance, and cost effectiveness. Often, the fine pitch layout poses great challenges to existing bump manufacture and flip chip assembly capability. This paper describes an advanced redistribution layer (RDL) solution for a tighter pitch die. A 10/10um L/S PBO RDL is applied to route a die that has two rows staggered 40/80um pitch pads into an area array flip chip format with 170um pitch. Initial construction analysis shows that this is a viable solution.