Automatic verification techniques, like automated theorem proving and model checking, cannot analyze large circuits due to the heavy requirements of memory and computational power. On the other hand, we can verify generic circuits, with universally quantified variables, using interactive theorem provers and thus overcome the above-mentioned limitations but at the cost of significant user guidance in the proof process. To facilitate this process and thus reduce the user involvement in the proofs, we recently proposed a higher-order-logic formalization of all the commonly used combinational circuits, like basic gates, adders, multiplier, multiplexers, demultiplexers, decoders and encoders, using the HOL4 theorem prover. In this project's paper, we describe this formally verified library and illustrate its utilization by verifying an n-bit arithmetic logic unit (ALU).
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