OPTIMIZED LOW-POWER SYNCHRONIZER DESIGN FOR THE IEEE 802.11a STANDARD

摘要

In this paper the authors propose a low-power synchronizer design for the IEEE 802.11a standard capable to estimate frequency offsets in the range ±468 kHz (80 ppm @ 5.8GHz) with very simple and effective frame detection and timing synchronization. The core area of the design after layout is 13 mm~(2), including the CORDIC and FFT processors, with a total estimated power consumption of 140 mW.