The best interface between CPUs and reconfigurable hardware in heterogeneous systems remains an open question. The trend in multi-core processors is to communicate through a shared memory hierarchy; but cache organizations that work best for general-purpose multi-core systems may not be best for heterogeneous systems. In this paper we explore a variety of cache topologies for connecting a CPU with reconfigurable hardware through a shared memory hierarchy. We demonstrate that in our modeled heterogeneous system, like in general multi-core systems, sharing at least one level of the cache is important for performance and multiple cache levels can reduce the dynamic power consumption of the memory hierarchy.
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