A shared, reconfigurable cache memory system is accessible to both a host processor or CPU and to one or more execution units. The execution unit is tightly coupled to the memory for concurrent execution under control of a local micro-coded controller. The controller executes micro-code stored in ROM, on board the controller or in the cache itself, and provides address generation. The cache combines SRAM and DRAM technologies to improve density and lower cost, while a 'look-ahead' read strategy maintains SRAM performance. The controller and micro-code provide control and parameters to the execution unit to support computation intensive tasks such as DSP without processor intervention. The described cache memory execution subsystem operates over a standard CPU or memory interface.
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