The main task of the interlock system is to preventany damage of the costly components of the RF station. Theimplementation of the interlock must also guarantee a maximumuninterrupted time of operation which implies theimplementation of self diagnostics and repair strategies on amodular basis. Additional tasks include collection and temporarystorage of status information of individual channels; transfer ofthis information to the higher level control system, and also theimplementation of slow control functions. The Interlock System incorporates a controller with severalslave modules for I/O processing. It implements the interlockfunction as hardwired logic (within a FPGA) and contains asoftcore processor for higher level tasks. The software performs asystem-test on power-up to check the hardware functionality andthe crate configuration. On success, the interlock hardware isconfigured for continuous operation. The architecture of the interlock system provides the fastprocessing of the incoming data and reaction in real timerequired for machine- and component-protection. Special fast front-end I/O and slave modules have beendeveloped to achieve the timing requirements. In addition slowinput signals without fast timing requirements are also processedby the central node of the interlock. For the processing of thesesignals there exist products on the market which are lessexpensive, already developed, easier to maintain, and have a longmarket history in comparison to our in-house solution. The integration of industrial products is possible by using astandard fieldbus protocol. For example, a possible solutionbased on a real time ethernet fieldbus will be discussed. It isimplemented with an "EtherCAT" master providing the I/Oextension to the interlock system for industrial components.
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