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A New Statistics-Based Online Baseline Restorer(SOBLR) for a High Count-Rate Fully DigitalSystem

机译:基于新的统计数据基准基准恢复器(SOBLR),用于高计数速率完全数字系统

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This study is to develop a novel, accurate, real-time digital baseline restorer using online statistical processingfor a high count-rate digital system such as positron emissiontomography (PET). In high count-rate nuclear instrumentationapplications, analog signals are DC-coupled for betterperformance. However, the detectors, pre-amplifiers and otherfront-end electronics would cause a signal baseline drift in aDC-coupling system, which will downgrade the performance ofenergy resolution and position accuracy. Event pileups normallyexist in a high-count rate system and the baseline drift willcreate errors in the event pileup-correction. Hence, a baselinerestorer (BLR) is required in a high count-rate system toremove the DC drift ahead of the pileup correction. Manymethods have been reported for BLR from classic analogmethods to digital filter solutions. However a single channelBLR with analog method can only work under 500KCPS count-rate, and normally a CMOS front-end ASIC is required for theapplication involved hundreds BLR such as a PET camera. Wehave developed a simple statistics-based online baseline restorer(SOBLR) for a high count-rate fully digital system, andhundreds SOBLRs can be implemented in one field-programmable gate array (FPGA). In this method, we acquireadditional samples, excluding the real gamma pulses, from theexisting free-running ADC in the digital system, and perform anonline statistical processing to generate a baseline value. Thisbaseline value will be subtracted from the digitized waveform toretrieve its original pulse with zero-baseline drift. This methodcan self-track the baseline without a micro-controller involved.The circuit consists of two digital counter/timers, onecomparator, one register and one subtraction unit. Simulationshows a single channel works at 30MCPS count-rate with pileupcondition. 336 baseline restorer circuits have been implementedin FPGA for our new fully digital PET system.
机译:这项研究是开发一种新型的,准确的,实时数字底线恢复使用在线统计processingfor高计数率的数字系统,如正电子emissiontomography(PET)。在高计数率核instrumentationapplications,模拟信号是直流耦合为betterperformance。然而,检测器,前置放大器和otherfront端电子将导致ADC耦合系统的信号基线漂移,这将降级ofenergy分辨率和位置精度的性能。事件pileups normallyexist在高计数率制度和基线漂移事件堆积校正willcreate错误。因此,baselinerestorer(BLR)在高计数率系统需要toRemove中DC漂移前方堆积的校正。 Manymethods已经报道了BLR从经典analogmethods数字滤波器解决方案。然而,随着模拟方法的单个channelBLR只能在500KCPS计数率工作,并且通常的CMOS前端ASIC需要theapplication涉及数百BLR诸如PET照相机。 Wehave开发了一种简单的基于统计的在线基线恢复器(SOBLR)为高计数率全数字系统,andhundreds SOBLRs可以在一个现场可编程门阵列(FPGA)来实现。在该方法中,我们acquireadditional样品,不含实伽玛脉冲,从在数字系统theexisting自由运行ADC,以及执行anonline统计处理,以产生一个基线值。 Thisbaseline值将从toretrieve其原始脉冲具有零基线漂移的数字化波形中减去。此methodcan自我跟踪基线无微控制器involved.The电路由两个数字计数器/定时器,onecomparator,一个寄存器和一个减法单元。 Simulationshows单通道工作在30MCPS计数率与pileupcondition。 336个基线恢复电路一直implementedin FPGA为我们新的全数字化的PET系统。

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