The fabrication of radiation tolerant devices is an emerging field with multiple applications in the space and high-energy physics domains. The reduction of radiation-induced oxide trapped charge characteristic of deep submicron CMOS processes can be boosted if appropriate layout styles such as the gate-enclosed layout transistors are used. In this paper we will present an analytical I-V model of these devices in both the linear and saturation regions of operation and a comparison to experimental data from fabricated devices.
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