Fast and simple modeling of non-rectangular transistors

摘要

As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability areemerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactureddespite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregulargates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangulargeometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed andsmoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methodseither model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; orthey are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simplesolution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of theequivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulationexperiments, we demonstrate that our model can accurately capture both on and off currents of the modeled non-rectangular gate device. The average error of our modeling approach is 1.6% for /on and 7.5% for loft.