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True Reticle cost saving by Multi Level Reticle approach

机译:通过多级掩盖方法确保真正的掩皮节省

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Today reticle costs become one of the main contributors in the cost of manufacturing of advanced logic products.Especially for low volume projects as of product sampling as well as design and product verifications the saving ofreticle costs becomes worthwhile. Multi level reticles are the combination of more then one lithographical layer on onephysical reticle. Due to this approach the physical amount of reticles per tape out will be reduced and thereby also thecosts for reticles will be significantly decreased. The multi level reticle approach is implemented as standard option inthe INFINEON Technologies tape out flow for advanced logic products. This means dependent on forecasted volumeand chip size it could be decided to tape out a project on multi level- or single level reticle. Technical setup, reticlelayout, specification, CAD flow and experience in daily work using multi level reticles in different design nodes will beshown. Reticle cost advantage versus reduced throughput will be discussed.
机译:今天,素质成本成为先进逻辑产品制造成本的主要贡献者之一。作为产品采样的低批量项目以及设计和产品验证,节省的储蓄成本变得有价值。多水分掩模是单透明掩模版上的更高一个光刻层的组合。由于这种方法,每胶带的物理量将减少,从而掩盖的睾丸将显着降低。多级掩模版方法实施为标准选项Inthe Infineon Technologies Tape Flow for Advanced Logic产品。这意味着依赖于预测的VolumeND芯片大小,可以决定将项目粘在多电平或单个级别掩模版上。在不同设计节点中使用多电平掩模的技术设置,ReticleLayout,规范,CAD流量和日常工作经验将Beshown。将讨论掩模版成本优势与降低的吞吐量。

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