The Optimization of Algorithm and Implementation for Dual-Constellation Navigation Receiver

摘要

Current dual-constellation GNSS navigation receiver can not fully satisfies the development of navigation industry. The architecture of current Compass and GPS dual-constellation navigation receiver is usually built upon FPGA and float-point DSP. Compared with fix-point DSP and FPGA, float-point DSP works slow and costs much, and it is also difficult to integrate float-point DSP into ASIC or ASSP. So in this paper, we discuss the optimized algorithm and the new implementation that integrate all parts of navigation receiver on one FPGA or ASIC.