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A Formal Method for Rapid SoC Prototyping

机译:一种快速SOC原型的形式方法

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摘要

In this paper a formal method is proposed, based on Attribute Grammars (AG), for rapid SoC prototyping. A generic platform is also proposed for the automatic SoC implementation of AG-based applications. The proposed system, given the specification of the application in the formalism of Attribute Grammars, automatically produces the necessary hardware modules for the syntactic and semantic analysis of input strings belonging to that grammar. The produced implementation tackles with the recognition task of the input string, using a hardware implementation of an extension of Earley's parallel parsing algorithm. Moreover, the system exhibits capabilities of inexactness. The attribute evaluation makes usage of a stack-based hardware. The hardware modules are described in Verilog Hardware Description Language (Verilog HDL) and synthesized in a Xilinx Virtex-5 ML506 FPGA. For the illustration of the proposed system, an example from the area of hardware compilers is given.
机译:在本文中,基于属性语法(AG),提出了一种形式的方法,用于快速SOC原型。还提出了一种通用平台,用于自动SOC实现AG基础应用。所提出的系统,鉴于属性语法的形式主义中应用程序的规范,自动为属于该语法的输入字符串的句法和语义分析产生必要的硬件模块。使用Earley的并行解析算法的扩展的硬件实现,使用输入字符串的识别任务来解决识别任务。此外,该系统表现出不精确的能力。属性评估使用基于堆栈的硬件。硬件模块在Verilog硬件描述语言(Verilog HDL)中描述,并在Xilinx Virtex-5 ML506 FPGA中合成。对于所提出的系统的插图,给出了来自硬件编译器区域的示例。

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