This paper presents a novel architecture for direct digital frequency synthesizer (DDFS) based on a modified parabolic polynomial interpolation method. A 16-segment parabolic polynomial interpolation is adopted to replace conventional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less fashion such that the speed can be significantly improved. The proposed DDFS is implemented in a standard 0.13 μm cell-based technology. The maximum clock rate is 227 MHz, and the core area is 0.25 mm2. The simulation result shows that the spurious free dynamic range (SFDR) is 117 dBc.
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机译：本文基于修改的抛物面多项式插值方法提出了一种用于直接数字频率合成器（DDFS）的新型架构。采用16段抛物线多项式插值来替换基于传统的基于ROM的相位幅度转换方法。此外，所提出的抛物线多项式插值以乘法器的方式实现，使得可以显着提高速度。所提出的DDFS以标准的0.13μm基于细胞的技术实施。最大时钟速率为227 MHz，核心区域为0.25 mm 2 。仿真结果表明，虚假的自由动态范围（SFDR）是117 DBC。
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