A New Approach for Nonlinearity Test of High Speed DAC

摘要

In this work, we propose a novel test scheme for high speed digital-to-analog converter (DAC) based on under-sampling technique. The under-sampling technique is constructed by a pulse-width-modulation (PWM) modulator. The DAC output signal is modulated through a low frequency sinusoidal carrier and converted to low speed pulse signal. The pulse width of low speed pulse signal can be measured using conventional logic analyzer and the nonlinearity error of DAC can be estimated by analyzing the variation of pulse width. An experiment on 8-bits 50～300MS/s DAC has shown very good result and only requires a set of instruments which have sample rate lower than that of the circuit-under-test (CUT).