This paper proposes a design method and programmable architectures for numerical function generators (NFGs) of two-variable functions. To realize a two-variable function in hardware, we partition a given domain of the given function into segments, and approximate the function by a polynomial in each segment. This paper introduces two planar segmentation algorithms that efficiently partition a domain of a two-variable function. This paper also introduces two architectures that can realize a wide range of two-variable Junctions. Our architectures allow a systematic design of two-variable junctions. FPGA implementation results show that, for a complicated function, our NFG achieves 58% of memory size and 39% of delay time of a circuit designed using one-variable NFGs.
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