Barrier synchronization for CELL multi-processor architecture

摘要

Cell microprocessor is a new multi-processors system, which has been used for consumer electronics, multimedia decoding/encoding, compress or uncompressing area. One important development technology for multi-processor system is barrier synchronization, which can improve the system performance if the appreciated barrier is adopted. Based three different communication mechanisms (mailbox, dma, and signal notification register) offered by CELL system, we implement three kinds of barrier implementation tools on the CELL multi-processor system. In the paper, we will show the implementation of barrier synchronization tools and compare the barriers from three aspects: spu size, performance, and synchronization information capacity.