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Model to Hardware Matching For nano-meter Scale Technologies

机译:用于纳米尺度技术的硬件匹配模型

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With technology scaling becoming ever more difficult, the drive to continue to deliver performance and density has led to increasing technology complexity. Examples include the pervasive application of resolution enhancement techniques (RET) to enable sub-wavelength lithography and achieve circuit density, and strain engineering to improve device mobility and achieve circuit performance. The result of this increasing technology complexity has been a corresponding increase in the complexity of design/technology interaction. This phenomena demonstrates itself as a drastic increase in the number and complexity of design rules. Many of these rules are the result of the increase of the number and magnitude of systematic effects. In addition to these systematic sources of variability, we have an increasing host of random variations such as line edge roughness, which impacts channel lengths, and random dopant fluctuations, which impact threshold voltage. The net result has been a reduction in our ability to reliably predict the outcome of the manufacturing process. Given that the integrated circuit design process is based completely on our ability to create computer models of the expected behavior of a design, this gap in predictability is a source of grave concern. Model to Hardware matching attempts to close this gap by developing techniques, tools, and design components which can be used to improve technology predictability.
机译:通过技术缩放变得更加困难,可以继续提供性能和密度的驱动力导致了越来越多的技术复杂性。示例包括分辨率增强技术(RET)的普及应用,以使子波长光刻和实现电路密度和应变工程来改善装置移动性并实现电路性能。这种越来越多的技术复杂性的结果是设计/技术相互作用复杂性的相应增加。这种现象展示了设计规则的数量和复杂性的剧烈增加。许多这些规则是增加系统效应的数量和数量的结果。除了这些系统的可变性来源之外,我们还具有增加的随机变化,例如线边缘粗糙度,其影响信道长度,以及冲击阈值电压的随机掺杂波动。净结果一直在减少我们可靠预测制造过程的结果的能力。鉴于集成电路设计过程是完全基于我们创建了设计的计算机模型的能力,可预测性的这种差距是严重关切的源泉。硬件匹配模型尝试通过开发可用于提高技术可预测性的技术,工具和设计组件来关闭此差距。

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