Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?

摘要

It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsic to nanoscale regimes and fundamentally limits the eventual benefits of the increased device density, i.e., the overheads associated with achieving fault-tolerance may counter the benefits of increased device density - density-reliability tradeoff. At the same time, as devices scale down one can expect a higher proportion of area to be associated with interconnection, i.e., area is wire dominated. This paper theoretically explores density-reliability tradeoffs in wire dominated integrated systems. We derive an area scaling model based on simple assumptions capturing the salient features of hierarchical design for high performance systems. We then evaluate overheads associated with using basic fault-tolerance techniques at different levels of the design hierarchy. This, albeit simplified model, allows us to tackle several interesting questions: When does it make sense to use smaller less reliable devices? At what scale of the design hierarchy should fault tolerance be applied in high performance integrated systems? Our analysis reveals two critical parameters, the technology and design scaling factors, which are key to predicting the reliability requirements for emerging technologies if traditional hierarchical design continues to be used.