High Defect Tolerant Low Cost Memory Chips

摘要

Memories are among the most dense integrated circuits fabricated, and so, have the highest rate of defects. This paper proposes a scheme for selecting the right redundancy in memory designs driven by the fabrication cost and the yield. It also proposes a new memory architecture that fills the gap between the existing all-or-none extremes with memories. Experiments show that the new scheme reduces cost by up to 70%.