A Methodology for Mapping SysML Activity Diagram to Time Petri Net for Requirement Validation of Embedded Real-Time Systems with Energy Constraints

摘要

In this paper we use the Activity diagram of the System Modeling Language (SysML) in combination with the new UML profile for Modeling and Analysis of Real-Time and Embedded systems (MARTE) in order to validate functional, timing and low power requirements in early phases of the embedded system development life-cycle. However, SysML lacks a formal semantics and hence it is not possible to apply, directly, mathematical techniques on SysML models for system validation. Thus, a novel approach for automatic translation of SysML Activity diagram into Time Petri Net with Energy constraints (ETPN) is proposed. In order to depict the practical usability of the proposed method, a case study is presented, namely, pulse-oximeter. Besides, the estimates obtained (execution time and energy consumption) from the model are 95% close to the respective measures obtained from the real hardware platform.