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FPGA-Based, Real-Time Simulation of Permanent Magnet Synchronous Motor Drive for Vehicular Applications

机译:基于FPGA的永磁同步电动机驱动的FPGA的实时仿真,用于车辆应用

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Presented is a real-time simulator of a permanent magnet synchronous motor (PMSM) drive implemented on an FPGA card. Real-time simulation of PMSM drives enable rapid deployment and thorough testing of control strategies in vehicular or industrial applications. The PMSM model is based on Park transform with a reference frame on the rotor and assumes sinusoidal flux induction. A 3-phase IGBT inverter drives the PMSM machine. Both models are implemented with the RT-LAB real-time simulation platform of Opal-RT Technologies using a Simulink blockset called Xilinx System Generator (XSG), and without any VHDL coding. The paper explains various aspects of the design of the motor drive models in fixed-point representation in XSG, as well as actual simulation validation against a standard PMSM drive model built in Simulink. The PMSM drive, along with a test source for the pulse width modulation, is coded for an FPGA card. The model has user-selectable dead time, modulation index, source angle offset, and frequency. The overall model compilation and simulation is entirely automated by RT-LAB. The drive can also run in a closed loop with a controller executing on a CPU of a real-time simulator. The final PMSM drive model runs with a 20-ns integration time step, allows for time multiplexing of d-q values, and has an I/O latency of 310 ns (250 ns for the PMSM machine alone). The drive is directly connected to RT-LAB digital inputs and analog outputs (1 microsecond settling time) on the FPGA card and has a resulting total hardware-in-the-loop latency of 1.31 microseconds.
机译:提出是在FPGA卡上实现的永磁同步电机(PMSM)驱动器的实时模拟器。 PMSM驱动器的实时仿真使车辆或工业应用中的控制策略的快速部署和彻底测试。 PMSM模型基于停放变换,具有转子上的参考框架,并呈现正弦助熔剂感应。 3相IGBT逆变器驱动PMSM机器。这两种模型都是使用称为Xilinx系统发生器(XSG)的Simulink SlockSet的Opal-RT技术的RT-Lab实时仿真平台实现,并且没有任何VHDL编码。本文介绍了XSG中的定点表示中的电机驱动模型的设计的各个方面,以及针对模拟中内置的标准PMSM驱动模型的实际模拟验证。 PMSM驱动器以及脉冲宽度调制的测试源进行编码,用于FPGA卡。该模型具有用户可选的死区时间,调制索引,源角偏移和频率。整体模型编译和仿真由RT-Lab完全自动化。驱动器还可以在闭环中运行,其使用在实时模拟器的CPU上执行的控制器。最终的PMSM驱动模型与20-NS积分时间步骤运行,允许时间复用D-Q值,并且具有310 ns的I / O等待时间(仅为PMSM机器250ns)。驱动器直接连接到FPGA卡上的RT-Lab数字输入和模拟输出(1微秒稳定时间),并产生了1.31微秒的总硬件in-in-loop-in-in-loop延迟。

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