Delay Constrained Register Transfer Level Dynamic Power Estimation

摘要

We present a top-down technique to estimate the average dynamic power consumption of combinational circuits at the register transfer level. The technique also captures the power-delay characteristics of a given combinational circuit. It uses the principles of logical effort to estimate the variation in capacitance, and a combination of existing techniques to estimate the variation in activity, over the delay curve of operation of the circuit. The technique does not involve post-estimation characterization and is applicable across technology nodes. The estimated power obtained from our method shows good accuracy with respect to the power obtained from a commercial gate-level power estimation tool.