SUB-30nm MOSFET FABRICATION TECHNOLOGY INCORPORATING PRECISE DOPANT PROFILE DESIGN USING DIFFUSION-LESS HIGH-ACTIVATION LASER ANNEALING

摘要

Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique. Two major features of the laser annealing (LA), i.e. diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional gate-length (L{sub}g) and effective gate-insulator thickness (T{sub}(inv)), maintaining sufficient current drivability prior to any local stress engineering applied, for instance, I{sub}(ON) =650/340[μA/μm] (nMOS/pMOS) at I{sub}(OFF)=100nA/μm, Vdd=0.9V, were obtained for sub-30nm L{sub}g (and also sidewall length) devices.